1. Field of the Invention
The present invention relates to a constant voltage generation circuit for generating a plurality of voltages and for selecting an optional voltage in the generated voltages and for outputting the selected voltage to outside, and more particularly, to a constant voltage generation circuit for generating a plurality of voltages and for rapidly selecting one of the generated voltages and for supplying a selected one to outside.
2. Description of Related Art
FIG. 5 is a circuit diagram showing a configuration of a conventional constant voltage generation circuit 78. In FIG. 5, the reference characters R51, R52, R53, and R54 designate resistors connected between nodes N51 and N55 in series to form a ladder resistor. The reference characters N51 and N55 denote nodes through which a voltage is supplied to each of the resistor R51 to R54. The reference characters N52, N53, and N54 indicate nodes providing voltages V2, V3, and V4 generated between the resistors R51 and R52, between the resistors R52 and R53, and between the resistors R53 and R54, respectively.
The reference characters SW51, SW52, and SW53 designate switches to select and to provide one of the voltages V2 to V4 at the nodes N52 to N54 to an output terminal OT by connecting the node N56 to one of the nodes N52 to N54. The reference character C51 denotes a parasitic capacitance connected to the node N56, the reference character N56 designates a node through which one of the voltages V2, V3, and V4 at the nodes N52, N53, and N54 selected by one of the switches SW51 to SW53 is provided to the output terminal OT. This reference character OT denotes an output terminal through which one of the voltages V2 to V4 is output to various devices (omitted from the drawing) that are located in following stages and connected to the conventional constant voltage generation device.
Next, a description will be given of the operation of the conventional constant voltage generation circuit.
FIGS. 6A and 6B is a timing chart showing the change of the voltage generated at the node N56 when one of the voltages at the nodes N52, N53, and N54 is supplied to the output terminal OT.
FIG. 6A shows the timing chart of the change of the voltage at the node N56 when the level of the voltage of the node N56 is risen from the voltage V4 to the voltage V3. FIG. 6B shows the timing chart of the voltage at the node N56 when the level of the voltage of the node N56 is fallen from the voltage V2 to the voltage V3.
Hereinafter, a description will be given of the operation of the conventional constant voltage generation circuit 78 in which the voltage at the node N56 is switched from the voltage V4 to the voltage V3 shown in FIG. 6A and also changed from the voltage V2 to the voltage V3 shown in FIG. 6B.
Firstly, as shown in FIG. 6A, a description will be given of the rising operation of a voltage level at the node N56 from the voltage V4 to the voltage V3.
In the case in which only the switch SW53 is in on state and both the switches SW51 and SW52 are in off state and the voltage at the node N56 is the voltage V4, when the switch SW53 turns off and the switch SW52 turns on in order to rise the voltage level at the node N56 to the voltage V3, the voltage at the node N56 will be risen by the voltage difference (V3-V4).
Because the node N56 has a parasitic capacitance C51, the parasitic capacitance C51 is also charged simultaneously when the node N56 is charged. That is, the time .DELTA.t1 to reach the voltage of the node N56 to a target level (this target level is the voltage V3 in the example shown in FIG. 6A) is the time required to charge the node N56 by the voltage difference (V3-V4), namely the time required to charge the node N56 by the magnitude of the change of the voltage at the node N56 because it is also required to charge the parasitic capacitance C51 in order to rise the level of the voltage at the node N56. In this case, the level of the voltage V3 of the node N56 is risen by a current flow from the node N53 to the node N56 immediately following the switch SW53 turns off and the switch SW52 turns on, and the level of the voltage V4 at the node N56 is the level before the switches SW53 turns off and SW52 turns on. That is, the magnitude of the time .DELTA.t1 depends on the magnitude of a current that flows to the node N56, and determined by the magnitude of the voltage difference (V3-V4), the magnitude of the parasitic capacitance C51, and loads in following stages (omitted from the diagram) connected to this conventional constant voltage circuit 78, during the charging operation.
Next, a description will be given of the operation shown in FIG. 6B when the level of the voltage at the node N56 is switched from the voltage V2 to the voltage V3 in the conventional constant voltage generation circuit 78 shown in FIG. 5.
First, when the voltage at the node N56 is the voltage V2 and the voltage at the node N56 is switched from the voltage V2 to the voltage V3 (namely, the decreasing of the voltage at the node N56), like the case shown in FIG. 6A, it must be required to discharge the voltage at the node N56 and the parasitic capacitance C51. The time .DELTA.t2 required to perform this discharging operation is equal to the time required for discharging the voltage difference between the voltage V3 and the voltage V2. In this case, the voltage V3 at the node N56 is obtained by a current flow from the node N56 to the node N53 caused immediately following the switch SW51 turns off and the switch SW52 turns on. The voltage V2 is the voltage at the node N56 before the switch SW51 turns off and the switch SW52 turns on. That is, the magnitude of the time .DELTA.t2 depends on the magnitude of a current that flows from the node N56 to the node N53, namely determined by the magnitude of the voltage difference (V3-V4) at the node N56, the magnitude of the parasitic capacitance C51, and loads in following stages (omitted from the diagram) connected to this conventional constant voltage circuit 78, during the discharging operation.
Thus, in the conventional constant voltage generation circuit 78 shown in FIG. 5, the time to switch the output voltage of the output terminal OT through which a voltage is supplied to outside is equal to a voltage difference at the output terminal OT before and after the voltage switching operation that is executed by a current flow from/to one node to/from the output terminal OT. That is, the time required for switching the level of the voltage of the output terminal OT is equal to the charging time required to charge the voltage at the node N56 (when the magnitude of the voltage at the output terminal OT is increased) or equal to the discharging time required for discharging the voltage at the node N56 (when the magnitude of the voltage at the output terminal OT is decreased).
During the charging operation, when the magnitude of the current determined by both the voltage difference in the voltage switching operation and a load connected to a current path is large, the time required to charge the output terminal OT including the parasitic capacitance C51 becomes short.
On the contrary, during the discharging operation, when the magnitude of the above current is large, the time required to discharge the output terminal OT including the parasitic capacitance C51 becomes short because the capacitances stored in both the output terminal OT and the parasitic capacitance C51 are rapidly discharged.
FIG. 7 is a diagram showing a configuration of an analogue/digital (A/D) converter (based on a method of successive comparison) incorporating the conventional constant voltage generation circuit 78 shown in FIG. 5.
In FIG. 7, the reference number 7 designates a path through which a control signal to indicate a reference time is transmitted. The operation of the A/D converter is performed based on the reference time 7. The reference number 78 indicates the conventional constant voltage circuit, as shown in FIG. 5, that inputs voltages of power sources through input terminals 1 and 2, and outputs a desired voltage. The reference number 9 denotes a comparator for comparing a comparison reference voltage 4 with a target voltage 3 for the comparison and for outputting a comparison result. The reference number 10 indicates a data storage circuit for inputting the comparison result and for storing it in order.
Hereinafter, a description will be given of the operation of the A/D converter based on a method of successive comparison incorporating the conventional constant voltage generation circuit 78 shown in FIG. 5.
When receiving the reference voltage 4 generated by and transferred from the constant voltage generation circuit 78, the comparator 9 compares the reference voltage 4 with the target voltage 3 for the comparison in magnitude. Then, the comparator 9 outputs the comparison result 6 to the data storage circuit 10. For example, when the target voltage 3 is greater than the reference voltage 4, the comparator 9 outputs the voltage whose magnitude is the same as that of the voltage of the power source. When it is smaller than the reference voltage 4, the comparator 9 outputs the voltage having the magnitude zero to the data storage circuit 10.
The data storage circuit 10 stores the comparison results transferred from the comparator 9 in the order of reception. That is, the data storage circuit 10 stores a first comparison result, a second comparison result, a third comparison result, . . . transferred from the comparator 9 in order. When the comparison result 6 is equal to the voltage of the power source, the data storage circuit 10 stores the data item "1" for the comparison result 6. When the comparison result 6 is the data "zero", the data storage circuit 10 stores the data item "0" for the comparison result 6. That is, because the data storage circuit 10 may store the comparison result from the comparator 9 by using a binary number "0" and "1", it is therefore possible to indicate the comparison result by using the binary number, "1" and "0" in digital form.
On the other hand, the comparison result 6 transferred from the comparator 9 is also transferred to the conventional constant voltage generation circuit 78 through a feedback path from the comparator 9 to the conventional constant voltage generation circuit 78. Following this, the conventional constant voltage generation circuit 78 outputs the reference voltage 4 for comparison that will be compared with the target voltage 3. The magnitude of this reference voltage 4 is determined based on the comparison result 6 transferred from the comparator 9.
For example, in order to indicate that the target voltage 3 is greater than the reference voltage 4 when the magnitude of the reference voltage 4 is a half (VCC/2) of the voltage VCC of the power source, the conventional constant voltage generation circuit 78 outputs a following reference voltage 4 whose magnitude becomes 3/4 VCC.
In order to indicate that the target voltage 3 is smaller than the reference voltage 4, the conventional constant voltage generation circuit 78 outputs a following reference voltage 4 whose magnitude becomes 1/4 VCC.
Thus, the reference voltage 4 output from the conventional constant voltage generation circuit 78 may be determined by using the comparison result 6 transferred from the comparator 6.
Furthermore, as described above, the reference number 7 designates the control signal to indicate a reference time. The A/D converter operates based on this control signal to indicate the reference time. That is, all of the data storage circuit 10, the conventional constant voltage generation circuit 78, and the comparator 9 incorporated in the A/D converter are performed in synchronization with the control signal. This guarantees the operation of the A/D converter.
There is an A/D converter disclosed in the Japanese patent application JP-A-62/258521 and the U.S. Pat. No. 4,794,374 that corresponds to the JP-A-62/258521 as another example of an A/D converter incorporating the conventional constant voltage generation circuit.
In this conventional example, a bias supply circuit and a fourth switch are placed at a common connection node between a first switch and a second switch incorporated in the A/D converter (a third switch is omitted from this explanation). By using the configuration, a parasitic capacitance belonging or associated with the common connection node may be charged or discharged forcibly and rapidly in a correction operation performed before a voltage switching operation. This configuration provides the conventional A/D converter capable of increasing the value of each resistance for voltage divider and more applicable to MOS integrated circuits having a low power consumption at a high speed rate and with a higher accuracy.
Because the conventional constant voltage generation circuit has the above configuration, when one level of the voltage is switched to another level of the voltage, the time required for the voltage switching operation is determined based on a voltage difference and the magnitude of a current flow when the switching operation of the voltage is performed. Thereby, when a current flowing through the output terminal of the conventional constant voltage generation circuit is small, there is a drawback that it takes a long time to switch the voltage of the output terminal. In addition, the conventional A/D converter discloses in the Japanese Patent Application JP-A-62/258521 has a larger hardware size and a larger power consumption because a bias voltage supply circuit is incorporated in each of a plurality of resistance sections located between a first power source and a second power source.